The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to organization of memory arrays for global bit-line architecture in high-performance semiconductor memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modem PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
As memory sizes continue to increase, satisfying the demands for high-speed access of memory arrays becomes increasingly difficult. Increasing memory sizes have been made possible in large part by continuing advances in semiconductor fabrication, i.e., placing more transistors and interconnect lines in the same die area. However, reduced dimensions of transistors leads to lower drive while reduced dimensions of interconnect lines leads to increased resistance. Managing this reduced drive and higher resistance through array organization thus becomes an important factor in providing high-speed access in high-performance memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate array architectures for high-performance memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Various embodiments of the invention have architectures suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Memory devices in accordance with the various embodiments of the invention include blocks of memory cells arranged in columns with each column of memory cells coupled to a main bit line. Such memory devices further include sector bit lines having multiple main bit lines coupled to each sector bit line through selective coupling devices, with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is coupled to a global bit line through a selective coupling device, with each global bit line coupled to more than one sensing device through the selective coupling devices. For embodiments having multiple sectors, the global bit lines may extend to more than one sector. The global bit lines are multiplexed and input to helper flip-flops for output to the data output registers of the memory device. This array organization permits tight packing of individual memory cells with high-speed access capabilities.
For one embodiment, the invention provides a memory array. The memory array includes a first memory block having columns of memory cells coupled to main bit lines of the first memory block, a second memory block having columns of memory cells coupled to main bit lines of the second memory block, sector bit lines coupled to main bit lines in both memory blocks, sensing devices coupled to the sector bit lines, and at least one global bit line selectively coupled to the sensing devices. Each sector bit line is selectively coupled to at least two main bit lines of each memory block.
For another embodiment, the invention provides a memory bank. The memory bank includes a first number of memory sectors each having a second number of memory blocks, each memory block having a third number of columns of non-volatile memory cells with each column of non-volatile memory cells coupled to a main bit line. The memory bank further includes a fourth number of sector bit lines in each memory sector, wherein each sector bit line extends to each memory block in its associated memory sector and wherein the fourth number is one-half the third number. The memory bank still further includes a plurality of block pass transistors, wherein one block pass transistor is coupled between each main bit line and a sector bit line to selectively couple each main bit line to a sector bit line, and wherein each main bit line is selectively coupled to only one sector bit line and each sector bit line is selectively coupled to two main bit lines in each memory block. The memory bank still further includes a plurality of sense amplifiers in each memory sector, wherein each sense amplifier is coupled to two sector bit lines in its associated memory sector, and a plurality of global bit lines, wherein each output of a sense amplifier is coupled to only one global bit line through a selective coupling device and each global bit line is coupled to an output of more than one sense amplifier in each memory sector of the memory bank through selective coupling devices.
For still another embodiment, the invention provides a memory array. The memory array includes at least one memory bank, each memory bank having at least one memory sector. Each memory sector includes at least two memory blocks, each memory block having columns of non-volatile memory cells coupled to a plurality of main bit lines and a plurality of sector bit lines, wherein each sector bit line extends to each memory block of its associated memory sector. Each memory sector further includes a plurality of block pass transistors coupled between each plurality of main bit lines and the plurality of sector bit lines to selectively couple each main bit line to a sector bit line, wherein each main bit line is selectively coupled to only one sector bit line of its associated memory sector and each sector bit line is selectively coupled to more than one main bit line of its associated memory sector. Each memory sector still further includes a plurality of sense amplifiers coupled to the plurality of sector bit lines, wherein each sense amplifier is coupled to two sector bit lines of its associated memory sector, and a plurality of global bit lines, wherein an output of each sense amplifier is selectively coupled to only one global bit line and each global bit line is selectively coupled to an output of more than one sense amplifier of each memory sector of its associated memory bank.
For a further embodiment, the invention provides a synchronous flash memory device. The memory device includes a plurality of memory banks containing non-volatile flash memory cells and a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks for synchronization to a system clock. Each memory bank includes a first number of memory sectors each having a second number of memory blocks, with each memory block having a third number of columns of non-volatile flash memory cells where each column of non-volatile flash memory cells is coupled to a main bit line. Each memory bank further includes a fourth number of sector bit lines in each memory sector, wherein each sector bit line extends to each memory block in its associated memory sector and wherein the fourth number is one-half the third number. Each sector bit line is selectively coupled to two main bit lines in each memory block while each main bit line is selectively coupled to only one sector bit line. Each memory bank further includes a plurality of sense amplifiers in each memory sector, wherein each sense amplifier is coupled to two sector bit lines in its associated memory sector, and a plurality of global bit lines, wherein an output of each sense amplifier is selectively coupled to only one global bit line and each global bit line is selectively coupled to an output of more than one sense amplifier in each memory sector of the memory bank.
The invention further provides methods and apparatus of varying scope.